Integrated circuits having a plurality of circuit elements on a single chip are commonplace in modern electronic devices. As is known in the art, one important aspect of the design and fabrication of such devices involves the ability to isolate the various elements to prevent interfering interactions between circuit elements on the same chip.
Shallow trench isolation (STI) is one technique for isolating metal-oxide-semiconductor (MOS) devices, and is preferred for certain applications because it results in a nearly flat surface. With STI, a nitride/oxide stack is used to mask the etching of silicon in a trench between devices. The trench is then filled with deposited oxide which is polished flat using a chemical mechanical polishing process. Following STI formation, and appropriate implant steps, a gate electrode is formed with lightly-doped drain (LDD) spacers on it.
In the prior art, the deposited oxide is nominally stoichiometric SiO.sub.2.
One problem associated with the prior art is that, at the end of the spacer oxide etch and during any intentional or unintentional overetch, the STI oxide is also exposed to the plasma. Most oxides etch at about the same rate in typical dielectric etch plasma, so the conventional STI fill-oxide accordingly recedes as a result of exposure to the plasma during spacer etch and overetch. See, e.g., FIG. 1, infra. A recess of 200-500 angstroms is typically observed under standard operating conditions, and a recess of that magnitude clearly degrades wafer planarity and compromises the advantages obtained by using STI for isolation.
A need therefore exists for a new technique for STI trench oxide deposition and spacer etch that will greatly reduce this recess. The present invention addresses that need.